1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods of controlling optical properties of a capping insulating layer on memory devices, and system for performing same.
2. Description of the Related Art
Memory devices such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), or flash erasable programmable read-only memories (FEPROMs) are, as their name indicates, erasable. Such erasable memory cells are used in a variety of different devices, e.g., digital cellular phones, digital cameras, LAN switches, cards for notebook computers, etc. A memory cell operates by storing electric charge (representing a digital “0” or “1” state) to an electrically isolated floating gate, which is incorporated into a transistor. This stored charge affects the behavior of the transistor, thereby providing a way to “read” the memory element. The switching speed of such a memory cell for converting from one state to the other state is limited in part by the speed of charge dissipation from the floating gate (i.e., the erase speed). Because faster erase speeds equate to faster switching speeds, efforts have been made to increase the erase speeds of such memory devices, as well as to improve the erase uniformity among the memory cells.
A flash memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically comprised of polycrystalline silicon (i.e., “polysilicon”), is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of silicon oxide. Because charge is transferred across the dielectric layer by quantum-mechanical tunneling, this dielectric layer is often referred to as a “tunnel oxide” layer. Such tunnel oxide layers are typically approximately 100 Å thick. Properties of the tunnel oxide must be strictly controlled to ensure the ability to read and write by tunneling, while avoiding data loss through charge trapping or leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as an oxide-nitride-oxide (ONO) stack.
Storing charge on the floating gate programs a memory cell. This is achieved via hot-electron injection by applying a high positive voltage (approximately 12V) to the control gate, and a high drain-to-source bias voltage (approximately 6V). An inversion region is created between the source and drain by the control gate voltage, and electrons are accelerated from the source to the drain by the drain bias voltage. Some fraction of these electrons will have sufficient energy to surmount the tunnel oxide barrier height and reach the floating gate. The floating gate is therefore programmed by collecting and storing these electrons to represent one digital state.
The negative charge captured in the floating gate makes the channel more positive and, thus, less conducting. As a result, the threshold voltage is higher for a charged cell than for an uncharged cell. Consequently, for a given voltage applied to the control gate, the non-volatile memory cell will conduct if the floating gate has no stored charge and will not conduct if the floating gate has stored charge. Therefore, a logical low or high is provided by the non-volatile memory cell based on whether or not the cell conducts at a given threshold voltage.
During the course of manufacturing integrated circuit products, such as memory products, microprocessors, ASICs, etc., various electrical charges may be stored on portions of the devices. For example, a charge may be inadvertently stored on the floating gate of a flash memory device. The undesirable charges may be the result of performing manufacturing processes that apply various voltages to the substrate and/or set up various electrical fields as part of the normal processing operations, e.g., processing tools that involve generating a plasma during the use of such tools.
To remove such undesirable charges from the product, the integrated circuit product is typically irradiated with ultraviolet (UV) light. This UV exposure process is typically performed to dissipate the undesirable charges prior to performing various electrical tests on the products to ensure that the products meet various electrical performance requirements. The ultraviolet light provides the stored electrons in the product with enough extra energy to dissipate through, for example, a word line of a memory product. However, this is a relatively time-consuming process. For example, after fabrication is completed, a wafer may be subjected to a UV erase process for a duration of approximately 8 minutes (two 4 minute cycles). Such UV erase processes are typically performed for a relatively long duration to accommodate a worst-case scenario as it relates to the magnitude of the stored charges and the optical characteristics and thicknesses of the capping layers. Such a process may lead to manufacturing inefficiencies and delay production. In some cases, excessive UV exposure may be detrimental to one or more operational aspects of the device.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.